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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. MAX1441 automotive, two-channel proximity and touch sensor 19-5310; rev 0; 7/10 general description the MAX1441 proximity and touch sensor ic is designed for capacitive proximity sensing in automotive passive remote keyless entry (prke) and other applications. this device provides signal processing to support two independent touch/proximity sensor channels. the device features two open-drain output pins with high- voltage capability up to 28v, as well as five digital i/os to indicate sensing events. during manufacturing, jtag programming uses four digital i/os. the device uses grounded electrode capacitive sens- ing to measure capacitance between one of the two sense pins and the ground. a hand approaching a sense electrode attached to these sense pins causes a change in measured capacitance indicating the presence (touch or proximity) of the object. active- guard outputs shield the sense electrode from unwant- ed sources without adding parasitic capacitance. spread-spectrum techniques in the sensor excitation circuit reduce both electromagnetic emissions and susceptibility to interfering signals. in addition, the sensing excitation frequency is programmable from 100khz to 500khz in 10khz steps to avoid interference. the sensor input signals are converted to a 12-bit digital data and are available to an on-chip microcon- troller ( f c). the device provides independent offset compensation of up to 63pf for each input channel. each channel can be programmed to 5pf, 10pf, or 20pf full-scale range. the device features an internal maxq ? microcontroller with 2kword of flash for user programs and 128 bytes of sram. this feature provides the ability to implement customized signal processing and discrimination algorithms that optimize performance in the systems. the device offers user-configurable general-purpose digital i/o lines. power-on-reset (por) circuitry provides consistent startup of the device, and a watchdog timer ensures long-term reliable operation of the users software. the device is available in a 20-pin tssop package and is specified over the -40 n c to +105n c automotive tem- perature range. features s low average operating current (100a at 14v) s 1.2.ff lsb capacitance-to-digital resolution (5pf range) s 5v to 28v operation s 45v overvoltage protection s sinusoidal excitation for reduced emi emissions s frequency spreading operation for reduced emi susceptibility and emissions s active-guard-sense architecture provides increased flexibility in system packaging s cmos/lvcmos-compatible outputs s embedded c supports user-specified adaptive sense algorithms s 2kwords flash memory s 128-byte sram s 2kv esd immunity on sensor i/o lines s jtag serial interface s supports two independent grounded capacitor sensor inputs s -12v reverse voltage protection with external diode applications prke system proximity sensing object detection systems ordering information + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. maxq is a registered trademark of maxim integrated products, inc. evaluation kit available part temp range pin-package MAX1441gup/v+ -40nc to +105nc 20 tssop
MAX1441 automotive, two-channel proximity and touch sensor 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (v dd = v aa , agnd = dgnd, unless otherwise noted.) v batt to agnd ..................................................... -0.3v to +45v v aa , v dd to agnd .................................................. -0.3v to +4v sinput1, sinput2, agud1, agud2 to agnd ................................... -0.3v to (v aa + 0.3v) reset , p0._, i.c. to dgnd ...................... -0.3v to (v dd + 0.3v) agnd to dgnd ................................................... -0.3v to +0.3v out1, out2, to agnd ......................................... -0.3v to +28v out_, p0._, continuous output current ........................ p 20ma continuous power dissipation (t a = +70 nc) single-layer pcb 20-lead tssop (derate 11mw/ n c above +70nc) ....... 879mw multilayer pcb 20-lead tssop (derate 13.6mw/ n c above +70nc) .. 1084mw junction-to-case thermal resistance ( b jc ) (note 1) 20-lead tssop ........................................................ +20nc/w junction-to-ambient thermal resistance ( b ja ) (note 1) single-layer pcb 20-lead tssop ........................................................ +91nc/w multilayer pcb 20-lead tssop ..................................................... +73.8nc/w operating temperature range ........................ -40n c to +105nc junction temperature ..................................................... +150nc storage temperature range ............................ -65n c to +150nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc electrical characteristics (v batt = 5v to 28v, v aa = v dd , t a = -40 n c to +105n c. typical values are at v batt = 14v, f ex = 300khz, t a = +25 n c, unless oth- erwise noted.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units average power-supply current 16ms capacitance-to-digital (c2d) con - version time, two active channels; cpu in sleep mode 100 120 fa capacitance-to-digital converter bit resolution 12 bits input capacitance range crng_[1:0] = 10 20 pf crng_[1:0] = 01 10 crng_[1:0] = 00 5 input capacitance lsb resolution 20pf capacitance range 4.8 ff 10pf capacitance range 2.4 5pf capacitance range 1.2 integral nonlinearity inl 1 %fs differential nonlinearity dnl 0.5 lsb sampling time f ex = 300khz (note 3) 584 600 624 fs number of effective bits 11 bits dc input current of sin1, sin2 300 na input capacitance excitation source source peak-to-peak voltage 300khz excitation frequency 0.96 1.0 1.21 v p-p minimum excitation frequency f exmin frequency control register = 0x0a (note 3) 100 khz maximum excitation frequency f exmax frequency control register = 0x32 (note 3) 500 khz
MAX1441 automotive, two-channel proximity and touch sensor 3 electrical characteristics (continued) (v batt = 5v to 28v, v aa = v dd , t a = -40 n c to +105n c. typical values are at v batt = 14v, f ex = 300khz, t a = +25 n c, unless oth- erwise noted.) (note 2) note 2: all units are production tested at t a = +25 n c and t a = +105 n c. limits over the operating temperature range are guaran- teed by design and characterization. note 3: measured indirectly by testing the excitation signal frequency. the excitation signal frequency is determined by the master oscillator frequency, which in turn determines the sample time. parameter symbol conditions min typ max units capacitive offset dacs offset adjustment range 6 bits 63 pf offset adjustment resolution 1 pf logic inputs/outputs (p0._, reset) output logic low v ol i sink = 2ma 0.4 v output logic high v oh i source = 2ma v dd - 0.5 v input logic low v il 3.0v < v dd < 3.6v 0.8 v input logic high v ih 3.0v < v dd < 3.6v 2.4 v leakage current i l i/o = high impedance 0.01 1 fa port 0 interrupt minimum pulse width 3.0v < v dd < 3.6v 20 ns high-voltage open-drain outputs (out1, out2) output logic low v ol2 i sink = 2ma 0.5 v leakage current i l v out1 = v out2 = 25v 1 fa microcontroller flash program memory size 16 bits wide 2k words program memory clear time t cpm 38 ms page write time t w 10 ms maximum flash erase/write cycles n cyc 100k cycles sram size 128 bytes cpu clock frequency f cpu 1.25 mhz internal oscillator oscillator frequency master oscillator 19.8 20.48 21.2 mhz rc oscillator 31.7 32 32.2 khz voltage regulator input voltage v batt 5 14 28 v maximum dropout voltage v drop i aa = 10ma 0.6 v quiescent current i q 8 fa output voltage v aa 5v < v batt < 28v, 0 < i aa < 10ma 3.2 3.4 3.6 v
MAX1441 automotive, two-channel proximity and touch sensor 4 typical operating characteristics (v batt = 14v, v aa = v dd = 3.4v, t a = +25nc, unless otherwise noted.) capacitance error vs. temperature MAX1441 toc01 temperature (c) capacitance error (% full scale) 100 75 25 50 0 -25 -0.8 -0.6 -0.4 -2.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -50 125 co_ = 0, 3.6pf input capacitance 5pf range 10pf range 20pf range capacitance error vs. parallel resistance (sinput_ to agud_) MAX1441 toc02 parallel resistance (i) capacitance error (% full scale) 10k 1k 100 -8 -6 -4 -2 0 2 -10 10 100k 10pf range, co_ = 8, 15pf input capacitance capacitance error vs. series resistance MAX1441 toc03 series resistance (i) capacitance error (% full scale) 10 -0.5 0 0.5 1.0 -1.0 1 100 10pf range, co_ = 8, 15pf input capacitance capacitance error vs. power-supply voltage MAX1441 toc04 power-supply voltage (v) capacitance error (% full scale) 25 20 10 15 -0.75 -0.50 -0.25 0 0.50 0.25 0.75 1.00 -1.00 5 5pf range, co_ = 0, 3.6pf input capacitance capacitance error vs. excitation frequency MAX1441 toc05 excitation frequency (khz) capacitance error (% full scale) 400 300 200 100 -2 -1 0 1 2 3 -3 0 500 20pf range co_ = 0, 3.6pf input capacitance for 5pf range, 7pf input capacitance for 10pf range, 14pf input capacitance for 20pf range 10pf range 5pf range total supply current vs. conversion period (one channel converting) MAX1441 toc06 conversion period (ms) total supply current (a) 14 12 8 10 4 6 2 100 150 200 250 300 350 400 450 500 50 0 16 cpu in stop mode total supply current vs. conversion period (two channels converting) MAX1441 toc07 conversion period (ms) total supply current (a) 14 12 8 10 4 6 2 100 150 200 250 300 350 400 450 500 50 0 16 cpu in stop mode ssb2 = 0x01 ssb2 = 0x1f ldo output voltage vs. load current MAX1441 toc08 load current (ma) v aa (v) 10 5 3.37 3.38 3.39 3.40 3.36 0 15 v batt = 28v v batt = 14v v batt = 5v ldo output voltage vs. temperature MAX1441 toc09 temperature (c) v aa (v) 100 75 50 25 0 -25 3.360 3.365 3.370 3.375 3.380 3.385 3.355 -50 125 v batt = 28v v batt = 14v v batt = 5v
MAX1441 automotive, two-channel proximity and touch sensor 5 typical operating characteristics (continued) (v batt = 14v, v aa = v dd = 3.4v, t a = +25nc, unless otherwise noted.) capacitance error vs. interference frequency offset MAX1441 toc10 interference frequency offset (khz) capacitance error (% full scale) 450 400 350 300 250 200 150 0 10 20 30 40 50 60 -10 100 500 10pf range, co_ = 8, 300khz excitation frequency, 500mv p-p interference frequency capacitance error vs. excitation bandwidth (with in-band interference) MAX1441 toc11 excitation bandwidth (khz) capacitance error (% full scale) 150 100 50 0 10 20 30 40 50 60 -10 0 200 10pf range, co_ = 8, 300khz excitation frequency, 300khz, 500mv p-p interference frequency output power vs. excitation frequency spectrum MAX1441 toc12 excitation frequency spectrum (khz) output power (dbm) 800 600 400 200 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1000 MAX1441 toc13 excitation bandwidth (khz) capacitance error (% full scale) 130 110 70 90 30 50 10 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 -10 150 capacitance error vs. excitation bandwidth 5pf range, co_ = 0, 3.6pf input capacitance detection distance vs. atxh register setting MAX1441 toc14 atxh register setting detection distance (mm) 30 25 15 20 10 5 0 35 10 20 30 40 50 60 70 80 90 100 0 25cm x 2cm touch pad 5pf range 20pf range 10pf range full-scale capacitance change vs. temperature MAX1441 toc15 temperature (c) full-scale capacitance change (% fs) 100 75 25 50 0 -25 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 -1.5 -50 125 5pf range 20pf range 10pf range
MAX1441 automotive, two-channel proximity and touch sensor 6 pin configuration pin description 20 19 18 17 16 15 14 1 2 3 4 5 6 7 v dd dgnd out1 out2 p0.1 / int1 / tdo p0. 2/ int2 / tdi p0.3 / tms p0.4 top view MAX1441 i.c. i.c. agud2 agud1 reset 13 8 sinput2 sinput1 12 9 agnd v aa 11 10 n.c. v batt p0. 0 / int0 / tck tssop pin name function 1 p0.4 cpu port 0 bit 4. digital input/output. 2 p0.3/tms cpu port 0 bit 3/tms. digital input/output. 3 p0.2/int2/tdi cpu port 0 bit 2/tdi. digital input/output with configurable edge-triggered interrupt. 4 p0.1/int1/tdo cpu port 0 bit 1/tdo. digital input/output with configurable edge-triggered interrupt. 5 p0.0/int0/tck cpu port 0 bit 0/tck. digital input/output with configurable edge-triggered interrupt. 6 reset active-low reset input. reset requires an external pullup to v dd . 7 agud1 active guard 1. driven guard (active shield) output for channel 1. 8 sinput1 sensor input 1. capacitive sensor electrode input for channel 1. 9 v aa analog power supply. v aa is internally connected to the output of an on-chip 3.4v linear regulator. connect v aa to v dd . bypass v aa with a 0.47 f f capacitor to agnd as close to v aa as possible. 10 v batt power-supply voltage. input to the 3.4v on-chip linear regulator. bypass v batt to agnd with a 0.1f f capacitor as close to v batt as possible. 11 n.c. no connection. not internally connected. leave n.c. unconnected. 12 agnd analog ground. connect agnd to dgnd. 13 sinput2 sensor input 2. capacitive sensor electrode input for channel 2. 14 agud2 active guard 2. driven guard (active shield) output for channel 2. 15, 16 i.c. internally connected. leave unconnected. 17 out2 open-drain output 2. cpu port 0 bit 6. 18 out1 open-drain output 1. cpu port 0 bit 5. 19 dgnd digital ground. connect dgnd to agnd. 20 v dd digital power supply. connect v dd to v aa . bypass v dd with a 0.47 f f capacitor to dgnd as close to v dd as possible.
MAX1441 automotive, two-channel proximity and touch sensor 7 functional diagram typical application circuit sinput1 sinput2 agud2 agud1 sinusoidal excitation generator communication and mode control port control c2d1 v batt v aa out1 out2 c2d2 clock generator offset comp 2 digital control block offset comp1 128 byte sram ldo 2-kword flash 2-kword rom maxq core MAX1441 p0.0 p0.1 p0.2 p0.3 p0.4 touch pads p0.0/ int0/ tck p0.1/ int1/ tdo p0.2/ int2/ tdi dgnd agnd reset p0.3/ tms sinput1 v batt v batt v dd v dd v aa v dd out1 out1 out2 out2 gnd programming pads agud1 4.7ki 10ki 10ki 0.47f 0.47f 0.1f agud2 sinput2 p0.4 MAX1441
MAX1441 automotive, two-channel proximity and touch sensor 8 detailed description the MAX1441 is a 2-channel proximity and touch sensor that contains all the functions necessary to implement a proximity/touch detection system for vehicle prke systems and other applications. there are four principal architectural components to the device: the capacitive sensing analog front-end (afe), a programmable cpu system, vehicle power, and i/o interface. figure 1 shows the jtag timing diagram. the afe uses a 2-channel c2d converter to measure the capacitance present between sensor inputs sinput1 and sinput2 and the ambient ground (figure 2). the afe-sensing architecture converts approaching hand motion to 12-bit digital words that are operated by an algorithm in the cpu to ensure detection of posi - tive events and minimizing false detections. the c2d converters can measure the input capacitance in three different ranges: 20pf, 10pf, and 5pf. additionally, the c2ds compensate up to 63pf of parasitic capacitance programmable in 1pf steps. in addition to capacitive proximity and touch detection, the afe contains por and a watchdog timer for monitor - ing cpu operations. the cpu runs the input capacitive data through an algorithm to ensure detection of positive events and minimizing false detections. the cpu system includes flash-based program memory, sram, clocks, and communications. the power input and signal out - puts provide a complete interface to the vehicle power system and a robust communication signal to remote electronic control modules (ecus). technical function each c2d converter produces an ac excitation voltage at inputs sinput1 and sinput2. the excitation voltage forces current through the capacitance connected to the sensor input. the current amplitude is proportional to the measured capacitance. the circuit measures the input capacitance by measuring the current flowing through the sensor inputs. this excitation signal is a sine wave with a frequency programmable from 100khz to 500khz in10khz steps. the sinusoidal excitation allows for much lower emi emissions compared to architectures that uti - lize simple square-wave excitation. the device drives the guard outputs agud1 and augd2 with the same signal from the sinusoidal excitation and shields the sense electrodes without adding parasitic capacitance. the converter measures the amplitude of the current and converts it to 12-bit digital data by a 12-bit c2d. the maximum conversion rate in each of the sensor channels is 1.66khz. the microcontroller reads the input capacitance values and uses a user-supplied custom algorithm to detect the object proximity. once the proximity is detected, figure 1. jtag timing diagram tck t 1 t 2 t 3 t 4 t 5 t 6 t 7 tdi, tms tdo
MAX1441 automotive, two-channel proximity and touch sensor 9 the microcontroller can use the out1 or out2 pins to signal the event to external modules. the gpios can also provide system or configuration inputs to the micro - controller. the device has a power-saving standby mode for power-sensitive applications. in the standby mode, the microcontroller is powered down (cpu stop mode) and the analog front-end runs conversions at a reduced and programmable rate. a programmable hardware discriminator monitors the c2d converters outputs and brings the device out of standby mode when a potential object-proximity event is detected. the microcontroller can then analyze the capacitance data and validate the object-proximity event. the on-chip watchdog timer requires periodic servicing from the microcontroller to ensure proper and continuous operation. the watchdog timer resets the microcontroller if it is not serviced. this prevents the microcontroller from permanently hanging up due to unpredicted code behavior. the device features an on-chip voltage regulator allowing the part to operate with a wide range of power-supply voltage inputs: 5v to 28v with protection up to 45v. the regulator provides power for all the circuits making the device a very compact single-chip solution. control registers the device's analog front-end is controlled by a number of control registers. the c2d conversion results and the afe status are accessible through status and result registers. all afe registers are available in the micro - controller data space. the control registers support read and write operations. the status and result registers are read-only registers. communication between the cpu and the external inter - face and afe registers is performed using read/write operations to cpu special-function registers (sfrs). the sfrs are organized in three sections (section iCsection iii); each section consists of six modules (m0Cm5). table 1 shows the location of each sfr within the sfr sections (see the detailed description for more details). sensed capacitance range the sensed capacitance range can be set independent- ly for both channels. after power-up, the range is set to 20pf in both channels. figure 2. capacitive-sensing function MAX1441 excitation: sinusoidal voltage source current flow into capacitance i c sensed object ground signal electric field
MAX1441 automotive, two-channel proximity and touch sensor 10 excitation frequency to avoid interference, the excitation frequency can be adjusted to automatically spread within a frequency range. the lower frequency bound and spread-spectrum bandwidth registers determine this range. spread spec - trum continuously changes the excitation frequency so that the radiated power is distributed over a frequency range rather than a single frequency. this lowers the radiated energy density and thus leads to a cleaner spectrum. in addition, by changing the excitation fre - quency, the capacitance measurement becomes more immune against interference signals. offset capacitance in case the capacitance measurement permanently reaches the upper or lower limit, there is a likelihood of a parasitic capacitance on top of the touch pads. this could be an ice coating on the door handle for example. in this case, the offset capacitance is adjusted so that the capacitance reenters the measurement range. a parasitic capacitance up to 63pf is compensated for each channel independently by properly setting the off - set registers, co1/co2. single conversion mode the c2d converter can be placed into a single conver - sion mode. in the single conversion mode, the micro - controller triggers a single conversion by setting bit sct. if the single conversion mode is enabled, the analog front-end powers up only during the conversion. scen controls the single conversion mode. scen = 1 enables the single conversion mode and scen = 0 disables the single conversion mode. when single conversion mode is enabled, set bit sct to trigger a conversion. sct bit automatically clears after the conversion is completed. standby control to save power, the analog front-end can be put in the standby state. during standby, the conversion rate is determined by the standby state conversion rate divider. sb controls the standby mode. sb = 1 enables the stand - by mode and sb = 0 disables the standby mode. there is only 1 sb bit common to both channels, so the channels cannot be placed in the standby state independently. the following sequence of control register writes to the pd register is recommended for entering standby mode: 1) set pd to 06h to put both afe channels into reset state. 2) write dsb and ssb2 registers to set standby rate (if not already set). 3) set pd to 00h to release afe reset. 4) set pd to 01h to enter standby mode. standby state conversion-rate divider the maximum c2d conversion rate is 1.66khz. standby state uses conversion-rate reduction to save power. the conversion rate divider and conversion rate subdivider determine the final conversion rate. the dsb divider dsb[4:0] is common to both sensor channels. the con - version rate for channel 2 can be further reduced by the ssb2[4:0] divider. the conversion rate in khz is deter - mined by the equation: conv,channel1 1 f 1.66khz d = conv,channel2 1 f 1.66khz d s = where d is an integer number determined by a 5-bit word dsb[4:0] and s is an integer number determined by a 5-bit word ssb2[4:0]. the default value of d and s is one. d > 1 when ssb2 > 1. table 1. important afe function registers register function crng adjust the capacitance range fel set the frequency of excitation feb set the bandwidth of the spread- spectrum modulation co1, co2 set the capacitance offset sct put the device in single-conversion mode dsb set the standby conversion rate ssb2 set the channel 2 standby conver - sion rate subdivider pd put the afe in power-down mode (does not affect cpu operation) wu1, wu2 select the wakeup criteria (rate-of- change and/or absolute capacitive change) at1h, at2h set the absolute wake-up thresh - old rt1h, rt2h set the capacitance rate-of- change threshold crslt1l, crslt1h channel 1 conversion result crslt2l, crslt2h channel 2 conversion result afeintst interrupt status of the afe
MAX1441 automotive, two-channel proximity and touch sensor 11 power-down control each sensor channel independently powers down through the pd register. bit value 1 powers down the channel and bit value 0 powers up the channel. the excitation source circuitry powers down if both chan - nels are powered down. powering down both channels also resets all afe internal circuits except for the afes control registers. wake-up event thresholds the sensor wakes up when the measured capacitance exceeds a set capacitance threshold and/or a pre - defined rate of change in the capacitance. when an object approaches the sensor, the sensed capacitance starts changing. once the capacitance value crosses the absolute value threshold and/or the capacitance rate of change crosses the rate-of-change threshold, the analog front-end is automatically put in the wake-up state and the sb bit is cleared. at the same time, the wake-up interrupt is sent to the microcontroller. the 8-bit word atx[11:4] determines the absolute wake-up threshold and 8-bit word rtx[11:4] determines the rate-of-change threshold. only the upper 8 bits are used in the thresh - old comparisons. bit aox determines if logical and or or operation is performed on the absolute and the rate-of-change threshold crossing events to produce the wake-up event. bit value 1 sets the and operation and bit value 0 sets or operation. both absolute and rate- of-change threshold crossing detection can be enabled or disabled using bits aex and rex. aex bit value 1 enables absolute value detection and rex bit value 1 enables rate-of-change detection. the thresholds can be independently programmed in channels 1 and 2. conversion result word the 12-bit result of the c2d conversion is available in crslt1l and crslt1h for channel 1 and in crslt2l and crslt2h for channel 2. bit ovrx is set to 1 if the cur - rent conversion caused overranging in the c2d converter. data ready in channel 1 the interrupt status bit idr1 is set to 1 when a new conversion result is available in channel 1. if the micro - controller does not read the conversion result before the next conversion is completed, the old conversion result is overwritten. data ready in channel 2 the interrupt status bit idr2 is set to 1 when a the new conversion result is available in channel 2. if the micro - controller does not read the conversion result before the next conversion is completed, the old conversion result is overwritten. wake-up event in channel 1 the interrupt status bit iwup1 is set to 1 when channel 1 detects a wake-up condition. wake-up event in channel 2 the interrupt status bit iwup2 is set to 1 when channel 2 detects a wake-up condition. detailed controller specification architecture the device is based on the maxq risc processor with harvard memory architecture. specific maxq special-purpose register implementation the device implements all other standard maxq special- purpose registers (sprs). for details, see the spr bit description in table 5. special-purpose registers table 2 summarizes the sprs and their address indexes. these registers can be accessed by user software. table 2. special-purpose register map module index of special-purpose register module specifier 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 ap 01000 ap apc psf ic imr sc iir ckcn wdcn a 01001 a0 a1 a2 a3 pfx 01011 pfx ip 01100 ip sp 01101 sp iv lc0 lc1 dpc 01110 offs dpc gr grl bp grs grh grxl fp dp 01111 dp0 dp1 cp
MAX1441 automotive, two-channel proximity and touch sensor 12 table 3. special-purpose register bit function indexes not specified in this table are either reserved for hardware functional use or for future expansion; access to these locations has deterministic behavior that may not be the intention of the user. register addresses high - lighted in the table are reserved. table 3 lists the spr registers functional bits and their bit positions. table 4 specifies the default reset condi - tion for all spr bits. the default value for unused spr bit locations is 0. for registers in the accumulator and loop module, all 16 bits are undetermined after a reset. undetermined values are labeled as i in the table. special default values are labeled as s in the table. table 5 details all sprs and their bit description. registers are also identified by their address in the form of (xxh, yyh), where xxh is the register index in hex and yyh is the module specifier in hex. register msb lsb ap [7:0] ap1 ap0 apc [7:0] clr ids mod1 mod0 psf [7:0] z s gpf1 gpf0 ov c e ic [7:0] ins ige imr [7:0] ims im1 im0 sc [7:0] tap rod pwl iir [7:0] iis ckcn [7:0] idle wdcn [7:0] por ewdi wd1 wd0 wdif wtrf ewt rwt a0 [15:0] a0[15:0] a1 [15:0] a1[15:0] a2 [15:0] a2[15:0] a3 [15:0] a2[15:0] pfx [15:0] pfx[15:0] ip [15:0] ip[15:0] sp [15:0] sp[15:0] iv [15:0] iv[15:0] lc0 [15:0] lc0[15:0] lc1 [15:0] lc1[15:0] dpc [7:0] wbs0 gr [15:0] gr[15:0] grl [7:0] grl[7:0] grs [15:8] gr7 gr6 gr5 gr4 gr3 gr2 gr1 gr0 [7:0] gr15 gr14 gr13 gr12 gr11 gr10 gr9 gr8 grh [7:0] grh[7:0] grxl [15:8] gr7 gr7 gr7 gr7 gr7 gr7 gr7 gr7 [7:0] gr7 gr6 gr5 gr4 gr3 gr2 gr1 gr0 dp0 [15:0] dp0[15:0]
MAX1441 automotive, two-channel proximity and touch sensor 13 table 4. special-purpose registers reset values table 5. special-purpose register bit description register msb lsb ap 0000 0000 apc 0000 0000 psf 1000 0000 ic 0000 0000 imr 0000 0000 sc 1000 00s0 iir 0000 0000 ckcn 1110 0000 wdcn ss11 0ss0 a0 0000 0000 0000 0000 a1 0000 0000 0000 0000 a2 0000 0000 0000 0000 a3 0000 0000 0000 0000 register msb lsb pfx 0000 0000 0000 0000 ip 1000 0000 0000 0000 sp 0000 0000 0010 1111 iv 0000 0111 1111 1101 lc0 0000 0000 0000 0000 lc1 0000 0000 0000 0000 dpc 0000 0000 0000 0100 gr 0000 0000 0000 0000 grl 0000 0000 grs 0000 0000 0000 0000 grh 0000 0000 grxl 0000 0000 0000 0000 dp0 0000 0000 0000 0000 register description ap (00h, 08h) accumulator pointer (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. ap[1:0] active accumulator select bits [1:0]. the setting of these bits activates one of the four accumulators in the accumulator module (a) to function as the active accumulator for arithmetic and logical opera - tions. the setting of these bits can be automatically incremented/decremented in a modulo fashion according to the setting to the apc register. ap[7:2] reserved. read returns 0. apc (01h, 08h) accumulator pointer control (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. apc[1:0]Cmod[1:0] modulo bits [1:0]. the accumulator pointer autoincrement/decrement function is activated when these bits are set to a value other than 00b. the modulo is selected accordingly when active pointer autoincre - ment/decrement is active. mod[1:0] modulo 00 default, no ap autoincrement/decrement 01 modulo 2 10 modulo 4 11 reserved (modulo 4 if set) apc[5:2] reserved. read returns 0. apc.6Cids increment/decrement select. when this bit is cleared to 0, the content of ap increments after an arith - metic or logical operation. when this bit is set to 1, the content of ap is decremented after arithmetic or logical operation. apc.7Cclr ap clear. when this bit is set to 1, the content of ap is cleared to 0. this bit automatically resets to 0 after clearing the ap register. note if the move apc, acc instruction (980ah) causes the clr bit to set, the clear operation overrides other functions (i.e., the ap autoincrement/decrement does not happen).
MAX1441 automotive, two-channel proximity and touch sensor 14 table 5. special-purpose register bit description (continued) register description psf (04h, 08h) processor status flags register (8-bit register) initialization this register is set to 80h on all forms of reset. read/write access unrestricted direct read. write access to ov, e, c, gpf1, and gpf0 bits only. psf.0Ce equal flag. this flag reflects the state of the equal bit of a compare operation. it is 1 when the two values are equal. it is 0 when the two values are different. writing a 1 to this bit by software is effectively set by the equal flag. psf.1Cc carry flag. this flag reflects the state of the carry bit of the active accumulator. its state may change after an arithmetic and logical operation. this flag is set to 1 if the last operation resulted in a carry/bor - row. otherwise, it is cleared to 0. writing a 1 to this bit by software is effectively set by the carry flag. psf.2Cov overflow flag. this flag is set to 1 if there is a carry out of bit 14 but not out of bit 15, or a carry out of bit 15 bit not out of bit 14 from the last arithmetic operation; otherwise, the ov remains as 0. when add - ing signed numbers, ov indicates a negative number resulted as the sum of two positive operands, or a positive sum resulted from two negative operands. for subtraction, ov is set if a borrow is needed into bit 14 but not into bit 15, or into bit 15 but not into bit 14. this bit can be read and written by software to allow it to be restored after events such as interrupt servicing and debug operations. psf.3Cgpf0 general-purpose flag 0. this is a general-purpose flag for software control. psf.4Cgpf1 general-purpose flag 1. this is a general-purpose flag for software control. psf.5 reserved. read returns 0. psf.6Cs sign flag. this flag reflects the state of the sign bit of the active accumulator (the most significant bit of the active accumulator). its state may change after an arithmetic and logical operation or after the switch of the active accumulator. when it is set to 1, it indicates a negative value in the active accumulator from the last operation. when it is cleared to 0, it indicates a positive value. psf.7Cz zero flag. this flag reflects the state of the zero bit of the active accumulator (bit-wise nor of the active accumulator). its state may change after an arithmetic and logical operation or after the switch of the active accumulator. when it is set to 1, it indicates a zero value as a result of the last operation. when it is cleared to 0, it indicates a nonzero value. ic (05h, 08h) interrupt and control register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. ic.0Cige interrupt global enable. the ige bit enables the interrupt handler if set to 1. no interrupt to the cpu is allowed if this bit is cleared to 0. ic.1Cins interrupt in service. the ins is set by the interrupt handler automatically when an interrupt is acknowledged. no further interrupt occurs as long as the ins remains set. the interrupt service routine can clear the ins to allow interrupt nesting. otherwise, at the execution of an reti/popi instruction, the ins is cleared automatically by the interrupt handler. ic[7:2] reserved. read returns 0. imr (06h, 08h) interrupt mask register (8-bit register) initialization this register is cleared 80h on all forms of reset. read/write access unrestricted read. all bits have unrestricted write access, unless otherwise stated. imr.0Cim0 interrupt mask 0. this bit is the module level interrupt enable for register module 0. to activate the interrupt request from module 0, the ige and im0 must be set and the ins is not set. clearing this bit to 0 disables all interrupt sources in module 0.
MAX1441 automotive, two-channel proximity and touch sensor 15 table 5. special-purpose register bit description (continued) register description imr.1Cim1 interrupt mask 1. this bit is the module level interrupt enable for register module 1. to activate the interrupt request from module 1, the ige and im1 must be set and the ins is not set. clearing this bit to 0 disables all interrupt sources in module 1. imr[6:2] reserved. read returns 0. imr.7Cims interrupt mask 7. this bit is the module level interrupt enable for spr modules. to activate the interrupt request from any spr modules, the ige and ims must be set and the ins is not set. clearing this bit to 0 disables all interrupt sources in all spr modules. this bit is read only and defaults to 1 on all forms of reset. sc (08h, 08h) system control register (8-bit register) initialization this register is set to 82h on por and set to 1000 00s0b on all other forms of reset. read/write access unrestricted read. see the following bit definition for write restriction. sc.0 reserved. read returns 0. sc.1Cpwl password lock. this bit defaults to 1 on a power-on reset. when this bit is 1, it requires a 32-byte password to be matched with the password in the program space before allowing access to the rom loaders utilities for read/write of program memory and debug functions. sc.2Crod rom operation done. this bit is used to signify completion of a rom operation sequence to the con - trol units. this allows the debug engine to determine the status of a rom sequence. setting this bit to logic 1 causes an internal system reset if the spe bit is also set. setting the rod bit clears the spe bit if it is set and the rod bit is automatically cleared by hardware once the control unit acknowledges the done indication. setting this bit to 1 causes either an internal system reset or the debug engine to execute a com - mand to clear this bit. either way, the applicable code is never able to read a 1 from this bit. sc[6:3] reserved. read returns 0. sc.7Ctap test access (jtag) port enable. this bit controls whether the test access port special function pins are enabled. the tap defaults to being enabled. clearing this bit to 0 disables the tap special function on the jtag pins. iir (0bh, 08h) interrupt identification register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted direct read. write access is a no operation. iir.0Cii0 interrupt id 0. when this bit is set to 1, it indicates that there is at least one pending interrupt in module 0. this bit is set only if the interrupt flag and its corresponding enable bit are set. the ii0 is cleared by hardware when the interrupt source is disabled or the flag is cleared by software. iir.1Cii1 interrupt id 1. when this bit is set to 1, it indicates that there is at least one pending interrupt in module 1. this bit is set only if the interrupt flag and its corresponding enable bit are set. the ii1 is cleared by hardware when the interrupt source is disabled or the flag is cleared by software. iir[6:2] reserved. read returns 0. iir.7Ciis interrupt id system. when this bit is set to 1, it indicates that there is at least one pending interrupt in spr modules. this bit is set only if the interrupt flag and its corresponding enable bit is set. the iis is cleared by hardware when the interrupt source is disabled or the flag is cleared by software. ckcn (0eh, 08h) system clock control register (8-bit register) initialization this register is set to 060h on all forms of resets. read/write access unrestricted read. see the following bit description for write restriction.
MAX1441 automotive, two-channel proximity and touch sensor 16 table 5. special-purpose register bit description (continued) register description ckcn[3:0] reserved. these bits are read only. read returns 0. ckcn.4Cstop stop mode select. setting this bit to 1 stops program execution and commences low-power cpu operation. this bit is cleared by a reset or any of the enabled external interrupts. setting and resetting the stop bit does not change the system clock source and its divide ratio. ckcn[6:5] reserved. these bits are read only. read returns 11b. ckcn.7Cidle idle mode select. setting this bit to a 1 stops program execution by halting the instruction pointer and disabling the internal module selects (similar to a nop operation). this provides a low-power mode that does not require a system warm-up on exit. wdcn (0fh, 08h) watchdog timer control (8-bit register) initialization this register is set to b2h on por and set to ss00 0ss0b on all other forms of reset. read/write access unrestricted read. unrestricted write access, unless stated otherwise. wdcn.0Crwt reset watchdog timer. setting this bit resets the watchdog timer count. this bit must be set before the watchdog timer expires, or a watchdog timer reset and/or interrupt is generated if enabled. the timeout period is defined by wd1 and wd0. this bit is always 0 when read. wdcn.1Cewt enable watchdog timer reset. setting this bit to 1 enables the watchdog timer to reset the device; clearing this bit to 0 disables the watchdog timer reset. it has no effect on the timer itself and its ability to generate a watchdog interrupt. this bit is set to 1 following a power-on reset and is unaffected by all other resets. this bit can only be written once by software. once written, the value of this bit is not altered by any subsequent write. wdcn.2Cwtrf watchdog timer reset flag. when set, this bit indicates that a watchdog timer reset has occurred. it is typically interrogated to determine if a reset was caused by the watchdog timer. it is cleared by power-on reset, but otherwise must be cleared by software before the next reset of any kind to allow software to work correctly. setting this bit by software does not generate a watchdog timer reset. if the ewt bit is cleared, the watchdog timer has no effect on this bit. wdcn.3Cwdif watchdog interrupt flag. this bit is set to 1 by a watchdog timeout, which indicates a watchdog timer event has occurred if ewt and/or ewdi are set. when the wdif is set, ewt and ewdi determine the action to take. setting this bit from 0 to 1 also activates the reset counter for the watchdog reset timeout, which allows 512 clock cycles for the system to reset the watchdog timer using the rwt bit. setting this bit in software generates a watchdog interrupt if enabled and triggers the reset counter. this bit must be cleared in software before exiting the interrupt service routine, or another interrupt is generated. the reset counter must be cleared by rwt once started. ewt ewdi wdif actions x x 0 no interrupt has occurred. 0 0 x watchdog disable, clock is gated off. 0 1 1 watchdog interrupt has occurred. 1 0 1 no interrupt has been generated. watchdog reset occurs in 512 clock cycles if rwt is not set or wdif not cleared. 1 1 1 watchdog interrupt has occurred. watchdog reset occurs in 512 clock cycles if rwt is not set or wdif not cleared. note: software cannot set this flag. software can only clear this flag. this restriction is specific to the MAX1441 only and does not apply to other maxq products.
MAX1441 automotive, two-channel proximity and touch sensor 17 table 5. special-purpose register bit description (continued) register description wdcn[5:4]Cwd[1:0] watchdog timer mode select bits [1:0]. these bits are used to provide a user selection of watchdog timer interrupt periods, which determine the watchdog timer interrupt timeout when the watchdog timer is enabled. all watchdog timer reset timeouts follow the programmed interrupt timeouts by 512 times the clock divide ratio oscillator cycles. mode select bit settings and the timeout values. changing the wd1:0 bit settings resets the watchdog timer unless the 512 clock reset counter has already started, in which case, changing the wd1:0 bits does not affect the watchdog timer or reset counter. these bits can only be written when simultaneously resetting the timer (rwt = 1). otherwise, a write to these control bits is ignored (i.e., user software sets the rwt bit and changes the wd value in the same instruction). wdcn.6Cewdi watchdog interrupt enable. setting this bit to 1 enables interrupt requests generated by the watchdog timer. clearing this bit to 0 disables the interrupt requests. this bit is cleared following a power-on reset and unaffected by all other resets. wdcn.7Cpor power-on reset flag. this bit indicates whether the last reset was a power-on reset. this bit is typically interrogated following a reset. it must be cleared before the next reset of any kind for software to work correctly. this bit is set following a power-on reset and unaffected by all other resets. a0 (00h, 09h) accumulator 0 (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. a0[15:0] accumulator 0 bits [15:0]. this register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. otherwise, it can be used as general-purpose working register. a1 (01h, 09h) accumulator 1 (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. a1[15:0] accumulator 1 bits [15:0]. this register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. otherwise, it can be used as a general-purpose working register. a2 (02h, 09h) accumulator 2 (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. a2[15:0] accumulator 2 bits [15:0]. this register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. otherwise, it can be used as a general-purpose working register. a3 (03h, 09h) accumulator 3 (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. a3[15:0] accumulator 3 bits [15:0]. this register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. otherwise, it can be used as a general-purpose working register.
MAX1441 automotive, two-channel proximity and touch sensor 18 table 5. special-purpose register bit description (continued) register description pfx (00hC07h, 0bh) prefix register (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. pfx[7:0] prefix register bits [7:0]. this register provides a means to supply the high-order byte of data to a 16-bit destination register with 8-bit sources. to transfer 8-bit source data to a 16-bit destination, the high-order byte must first transfer to the pfx register. this activates the pfx for the next instruction cycle, which concatenates pfx data with the source operand to form a 16-bit data for the target destination. the pfx holds data for only one cycle before resetting all its bits to 0. when pfx is used as a source, it basically transfers a zero value to the destination when pfx has not been activated in the preceding instruction. pfx[15:8] prefix register bits [15:8]. reserved. read returns 0. note: subdecodes (1hC7h) function as extension bits for source/destination indexing. ip (00h, 0ch) instruction pointer (16-bit register) initialization this register is set to 8000h on all forms of reset. read/write access unrestricted read/write. ip[15:0] instruction pointer bits [15:0]. this register contains the next program address to be fetched by the fetch unit. the content of ip is automatically incremented by 1 after each fetch. new data written to this register causes the program flow to branch to the new location. read access to the ip register does not affect the program flow. sp (01h, 0dh) stack pointer (16-bit register) initialization this register is cleared to 002fh on all forms of reset. read/write access unrestricted read/write. sp[5:0] stack pointer bits [5:0]. the sp designates the memory location that is at the top of the stack, which is the storage location of the last word. the contents of the sp is postdecremented for a pop operation, and is preincremented for a push operation. sp[15:6] reserved. read returns 0. iv (02h, 0dh) interrupt vector register (16-bit register) initialization this register is set to 07fdh on all forms of reset. read/write access unrestricted read only. iv[15:0] interrupt vector bits [15:0]. this register contains the interrupt vector address. the interrupt handler forces a hardware call to this vector location when there is an enabled interrupt request pending. lc0 (06h, 0dh) loop counter 0 (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. lc0[15:0] loop counter 0 bits [15:0]. this register contains the loop count for a loop operation. the content of lc0 is automatically decremented by 1 after each loop. this register is normally used as a loop control for conditional branch to a new location. lc1 (07h, 0dh) loop counter 1 (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. lc1[15:0] loop counter 1 bits [15:0]. this register contains the loop count for a loop operation. the content of lc1 is automatically decremented by 1 after each loop. this register is normally used as loop control for conditional branch to a new location.
MAX1441 automotive, two-channel proximity and touch sensor 19 table 5. special-purpose register bit description (continued) register description dpc (04h, 0eh) data pointer control register (16-bit register) initialization this register is set to 0004h on all forms of reset. read/write access unrestricted read/write. dpc[1:0]Csdps[1:0] reserved. read returns 0. dpc.2Cwbs0 word/byte select 0. this bit selects access mode for dp[0]. when wbs0 is set to logic 1, the dp[0] is operated in word mode for data-memory access; when wbs0 is cleared to logic 0, dp[0] is operated in byte mode for data-memory access. dpc[15:3] reserved. read returns 0. gr (05h, 0eh) general register (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. gr[15:0] general register bits [15:0]. this register is intended primarily for supporting byte operation on 16-bit data. gr can be used as a 16-bit general-purpose register and allows byte-readable and byte-writable operations through the corresponding grl and grh register locations. it also supports byte-swap operation when read through the grs register location. grl (06h, 0eh) general register low byte (8-bit location) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. grl[7:0] general register low byte bits [7:0]. this register location reflects the low byte of the gr register and is intended primarily for supporting byte operation on 16-bit data. any data written to this location stores in the low byte of the gr register, and a read in this location returns the least significant data byte of the gr register. grs (08h, 0eh) general register byte swap (16-bit location) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read only. grs[15:0] general register byte swap bits [15:0]. this read-only register location reflects the byte-swapped data of the gr register and is intended primarily for supporting byte operation on 16-bit data. reading this register location returns the byte-swapped data from the gr register. grh (09h, 0eh) general register high byte (8-bit location) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. grh[7:0] general register high byte bits [7:0]. this register location reflects the high byte of the gr register and is intended primarily for supporting byte operation on 16-bit data. any data written to this location stores in the high byte of the gr register, and read this location returns the most significant data byte of the gr register. grxl (0ah, 0eh) general register sign extended low byte (16-bit location) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read only. grxl[15:0] general register sign extended byte bits [15:0]. this read-only register location reflects the sign extended low byte of the gr register. when read, the upper 8 bits contain the logic value of bit 7 of the gr register, and the lower 8 bits are the low byte of the gr register.
MAX1441 automotive, two-channel proximity and touch sensor 20 special-function registers all peripherals and operations that are not explicit instructions in the device are controlled using special- function registers (sfrs). these registers allow commu - nication and data exchange between the cpu and the peripherals. normally, interaction between a peripheral and the processor is initiated through the interrupt han - dler. sfrs can be 8-bit or 16-bit registers and most of the sfrs are accessible by user software (tables 6, 7, 8). all undefined or unallocated registers should be treated as reserved registers. table 5. special-purpose register bit description (continued) table 6. special-function register map section i table 7. special-function register map section ii table 8. special-function register map (section iii) register description dp0 (03h, 0fh) data pointer 0 (16-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. dp0[15:0] data pointer 0 bits [15:0]. this register contains the data address for data memory access. the contents of dp0 can be automatically incremented/decremented for read/write data-memory operation. module index of special-function register (section i) m[x] specifier 00000 00001 00010 00011 00100 00101 00110 00111 m0 00000 po0 eif0 eie0 eies0 tcon tfrq tcnt m1 00001 afeintst sct crng pd wu1 wu2 fel feb m2 00010 m3 00011 m4 00100 m5 00101 module index of special-function register (section ii) m[x] specifier 01000 01001 01010 01011 01100 01101 01110 01111 m0 00000 pi0 pd0 tm2 brkp m1 00001 crslt1l crslt1h crslt2l crslt2h at1h rt1h at2h rt2h m2 00010 m3 00011 m4 00100 m5 00101 module index of special-function register (section iii) m[x] specifier 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 m0 00000 lock icdt0 icdt1 icdc icdf icdb icda icdd m1 00001 co1 co2 dsb ssb2 afeie m2 00010 m3 00011 m4 00100 m5 00101
MAX1441 automotive, two-channel proximity and touch sensor 21 table 9 lists the sfr registers functional bits and their bit positions. table 10 specifies the default reset condition for all sfr bits. special default values are labeled as s in the table. the default value for unused sfr bit locations is 0. table 11 details all sfrs and their bit description. registers are also identified by their address in the form of (xxh, yyh), where xxh is the register index in hex and yyh is the module specifier in hex. table 9. special-function register bit function register msb lsb module 0 po0 [7:0] po0[6:0] eif0 [7:0] ie[2:0] eie0 [7:0] ex[2:0] eies0 [7:0] it[2:0] tcon [7:0] tmrie tmrif tvalid tmren tclk tpss[2:0] tfrq [7:0] tfrq[7:0] tcnt [7:0] tcnt[7:0] pi0 [7:0] pi0[6:0] pd0 [7:0] pd0[6:0] brkp [15:0] break icdt0 [15:0] icdt0[15:0] icdt1 [15:0] icdt1[15:0] icdc [7:0] dme cmd3 cmd2 cmd1 cmd0 icdf [7:0] pss1 pss0 jspe txc icdb [7:0] icdb[7:0] icda [15:0] icda[15:0] icdd [15:0] icdd[15:0] module 1 afeintst [7:0] iwup2 iwup1 idr2 idr1 sct [7:0] scen sct crng [7:0] crng2 [1:0] crng1 [1:0] pd [7:0] pd2 pd1 sb wu1 [7:0] ao1 re1 ae1 wu2 [7:0] ao2 re2 ae2 fel [7:0] fel[5:0] feb [7:0] feb[4:0] crslt1l [7:0] crslt1[3:0] ovr1 crslt1h [7:0] crslt1[11:4] crslt2l [7:0] crslt2[3:0] ovr2 crslt2h [7:0] crslt2[11:4] at1h [7:0] at1[11:4] rt1h [7:0] rt1[11:4] at2h [7:0] at2[11:4] rt2h [7:0] rt2[11:4] co1 [7:0] co1[5:0] co2 [7:0] co2[5:0] dsb [7:0] dsb[4:0] ssb2 [7:0] ssb2[4:0] afeie [7:0] eiwup2 eiwup1 edr2 edr1
MAX1441 automotive, two-channel proximity and touch sensor 22 table 10. special-function register reset values table 11. special-function register bit description module 0 module 1 register msb lsb register msb lsb po0 0111 1111 afeintst 0000 0000 eif0 0000 0000 sct 0000 0010 eie0 0000 0000 crng 0010 0010 eies0 0000 0000 pd 0000 0000 tcon 0000 0000 wu1 0000 0100 tfrq 0000 0000 wu2 0000 0100 tcnt 0000 0000 fel 0001 1110 pi0 ssss ssss feb 0000 0000 pd0 0000 0000 crslt1l 0000 0000 brkpnt 0000 0000 0000 0000 crslt1h 0000 0000 icdt0 0000 0000 0000 0000 crslt2l 0000 0000 icdt1 0000 0000 0000 0000 crslt2h 0000 0000 icdc 0000 0000 at1h 0000 0000 icdf 0000 0000 rt1h 0000 0000 icdb 0000 0000 at2h 0000 0000 icda 0000 0000 0000 0000 rt2h 0000 0000 icdd 0000 0000 0000 0000 co1 0000 0000 co2 0000 0000 dsb 0000 0001 ssb2 0000 0001 afeie 0000 0000 register description po0 (00h, 00h) port 0 output register (8-bit register) initialization this register is set to 7fh on all forms of reset. read/write access unrestricted read/write. po0[6:0] port 0 output register bits [6:0]. this register stores output data for this port when it is defined as an output port. reading from the register returns the contents of the register and does not necessarily reflect the true state of the port pins. changing the direction of this port does not change the data con - tents of the register. po0.7 reserved. read returns 0. eif0 (01h, 00h) external interrupt flag 0 register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. eif0[2:0]Cie[2:0] interrupt edge detect bits [2:0]. these bits are set when the edge selected by itx is detected on the interrupt pin, intx. setting any of the bits to 1 generates an interrupt to the cpu if the corresponding interrupt is enabled. these bits remain set until cleared by software or a reset. it must be cleared by software before exiting the interrupt source routine or another interrupt is generated as long as the bit remains set. eif0[7:3] reserved. read returns 0.
MAX1441 automotive, two-channel proximity and touch sensor 23 table 11. special-function register bit description (continued) register description eie0 (02h, 00h) external interrupt enable 0 register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. eie0[2:0]Cex[2:0] enable external interrupt bits [2:0]. setting any of these bits to 1 enables the corresponding external interrupt, intx. clearing any of the bits to 0 disables the corresponding interrupt function. eie0[7:3] reserved. read returns 0. eies0 (03h, 00h) external interrupt edge select 0 register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. eies0[2:0]Cit[2:0] edge select for external interrupt bits [2:0]: itx = 0 C external interrupt intx is positive edge triggered. itx = 1 C external interrupt intx is negative edge triggered. eif0[7:3] reserved. read returns 0. tcon (04h, 00h) timer control register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read. write is unrestricted, unless otherwise stated in the following bit description. tcon[2:0]Ctpss[2:0] timer prescaler select bits [2:0]. the following bits select the prescaler value that apply to the select source clock. tpss[2:0] prescale value 000 /1 001 /4 010 /16 011 /64 100 /256 101 /512 110 /1024 111 /2048 these bits can only be written to when the timer is disabled (tmren = 0). tcon.3Ctclk timer clock select. this bit selects the clock source used by the timer. when this bit is cleared to 0, the system clock is used as the clock source. when this bit is set to 1, the 32khz is used. this bit can only be written to when the timer is disabled (tmren = 0). tcon.4Ctmren timer enable. setting this bit to 1 enables the timer. clearing this bit halts the timer. the timer contin - ues to run in stop mode if tmren = 1. tcon.5Ctvalid timer value valid. this bit indicates whether tcnt returns the valid value when 32khz is selected as the clock source. when this bit is set to 1, tcnt returns the valid value. when this bit is cleared to 0, tcnt returns 0000h. this bit has no meaning when the system clock is used as a clock source. in this case, tcnt always returns valid value. tcon.6Ctmrif timer interrupt flag. this bit is set to 1 when the timer count matches the timer frequency value. it is cleared either by software or a reset. a 0 on this bit indicates no timer overflow has been detected. tcon.7Ctmrie timer interrupt enable. setting this bit to 1 enables the timer interrupt. clearing this bit to 0 disables the timer interrupt.
MAX1441 automotive, two-channel proximity and touch sensor 24 table 11. special-function register bit description (continued) register description tfrq (05h, 00h) timer frequency register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read. this register can only be written when tclk = 0; otherwise, a write to this register is ignored. tfrq[7:0] timer reload register bits [7:0]. this register is used to store timer overflow value. tcnt (06h, 00h) timer count register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read. this register can only be written when tclk = 0; otherwise, a write to this register is ignored. tcnt[7:0] timer count register bits [7:0]. this register is used to load and read a value to/from the timer. pi0 (08h, 00h) port 0 input register (8-bit register) initialization the reset value for this register is dependent on the logical states of the pins. read/write access unrestricted read only pi0[6:0] port 0 input register bits [6:0]. this register reflects the logic state of its port pins when read. pi0.7 reserved. read returns 0. pd0 (09h, 00h) port 0 direction register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. pd0[6:0] port 0 direction register bits [6:0]. this register is used to determine the direction of the port 0 function. the port pins are independently controlled by their direction bits. when a bit is set to 1, its corresponding pin is used as an output; data in the po register is driven on the pin. when a bit is cleared to 0, its corresponding pin is used as an input, and allows an external signal to drive the pin. note that when functioning as an input, the port pin is driven to a high-impedance state. pd0.7 reserved. read returns 0. brkp (0fh, 00h) software breakpoint register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. brkp.0Cbreak break. setting this bit causes an emulation breakpoint to activate and halt the system on the instruction, which sets the bit. this bit is connected directly to the sbpe input on the emulation block and is self-clearing. a read of this bit always returns zero. brkp[7:1] reserved. read returns 0. icdt0 (18h, 00h) in-circuit debug temp 0 register (16-bit register) initialization this register is cleared to 0000h after a power-on reset or a test-logic-reset tap state. read/write access unrestricted read/write access by the cpu from background, debug, or test (tme = 1) mode. icdt0[15:0] in-circuit debug temp 0 register bits [15:0]. this register is intended for use by the utility rom in-circuit debug or test routines as temporary storage to save registers that might otherwise have to be placed in the stack (e.g., dpc, dp[n]). icdt1 (19h, 00h) in-circuit debug temp 1 register (16-bit register) initialization this register is cleared to 0000h after a power-on reset or a test-logic-reset tap state. read/write access unrestricted read/write access by the cpu from background, debug, or test (tme = 1) mode. icdt1[15:0] in-circuit debug temp 1 register bits [15:0]. this register is intended for use by the utility rom in-circuit debug or test routines as temporary storage to save registers that might otherwise have to be placed in the stack (e.g., dpc, dp[n]).
MAX1441 automotive, two-channel proximity and touch sensor 25 table 11. special-function register bit description (continued) register description icdc (1ah, 00h) in-circuit debug control register (8-bit register) initialization this register is cleared to 00h after a power-on reset or a test-logic-reset tap state. read/write access unrestricted read; all bits are set and cleared by the debug engine only. this register can be accessed using a valid jtag debug engine command. icdc[3:0]Ccmd[3:0] command bits [3:0]. these bits reflect the current host command in debug mode. these bits are set by the debug engine and allow the rom code to determine the course of action. cmd[3:0] action 0000 no operation 0001 read register 0010 read data memory 0011 read stack memory 0100 write register 0101 write data memory 0110 trace, single step the cpu 0111 return, return to background mode 1000 unlock password 1001 read selected register 1010 execute test execute test (only supported when tme = 1) other reserved icdc.4 reserved. read returns 0. icdc.5Crege break-on register enable. this bit always returns 0. therefore, bp4 and bp5 breakpoints are not supported. icdc.6Cte timer enabled. this bit always returns 0 and the timer is automatically disabled in debug mode. icdc.7Cdme debug mode enable. when this bit is cleared to 0, background mode commands can be executed but breakpoints are disabled. when this bit is set to 1, breakpoints are enabled while background mode commands can still be entered. this bit is only set or cleared from background mode. this bit has no meaning for the rom code. icdf (1bh, 00h) in-circuit debug flag register (8-bit register) initialization this register is cleared to 00h after a power-on reset or a test-logic-reset tap state. read/write access unrestricted read; only bit 0 is writable by the cpu. icdf.0Ctxc serial transfer complete. this bit is set by the hardware at the end of a transfer cycle at the tap communication link. the txc helps the debug engine to recognize host requests, either command or data. this bit is normally set by rom code to signify/request sending or receiving data; the txc must be cleared by the debug engine once set. cpu writes to the txc bit result in clearing the jtag pss1:0 bits. icdf.1Cspe system program enable. the spe bit used for in-system programming support and its logical state, when read by the cpu, always reflects the logical-or of the spe bit and the spe bit of the system programming buffer (spb) register in the tap module (which is accessible using jtag). the logical state of this bit determines the program flow after a reset. when it is set to logic 1, in-system program - ming is executed by the utility rom. when it is cleared to 0, execution is transferred to user code. this bit allows read access by the cpu and is cleared to 0 only on a power-on reset or test-logic-reset. the jtag spe bit is cleared by hardware when the rod bit is set. the spe bit is read only.
MAX1441 automotive, two-channel proximity and touch sensor 26 table 11. special-function register bit description (continued) register description icdf[7:2] reserved. read returns 0. icdb (1ch, 00h) in-circuit debug buffer register (8-bit register) initialization this register is cleared to 00h after a power-on reset or a test-logic-reset tap state. read/write access unrestricted read/write by cpu. icdb[7:0] in-circuit debug buffer bits [7:0]. icdb serves as the parallel holding buffer for the debug shift register of the tap. data is read from or written to icdb for serial communication between the debug function and the external host. this register is mapped to the sfr space for read/write access by the cpu. icda (1dh, 00h) in-circuit debug address register (16-bit register) initialization this register is cleared to ffffh after a power-on reset or a test-logic-reset tap state. read/write access unrestricted read by the cpu. this register can be accessed using a valid jtag debug engine command. icda[15:0] in-circuit debug address bits [15:0]. this register serves as the address register for the debug engine to store a specific location for the rom code execution. this register is also used by the debug engine as a mask register to mask out dont care bits in the icdd register when bp5 is used as a register breakpoint. when a bit in this register is set to 1, the corresponding bit location in the icdd register is compared to the updating destination data to determine if a break should be generated. when a bit in this register is cleared, the corresponding bit in the icdd register becomes a dont care and is not compared against the updating data. when all bits in this register are cleared, any updated data pattern causes a break when the bp5 register matches the destination register address of the current instruction. icdd (1eh, 00h) in-circuit debug data register (16-bit register) initialization this register is cleared to 0000h after a power-on reset or a test-logic-reset tap state. read/write access unrestricted read by the cpu. this register can be accessed using a valid jtag debug engine command. icdd[15:0] in-circuit debug data bits [15:0]. this register serves as the data/count register for the debug engine to store data or read count for rom code execution. this register is also used by the debug engine as a data register for content matching when bp5 is used as a register breakpoint. in this case, only data bits in this register with their corresponding mask bits in the icda register set is compared with the updated destination data to determine if a break should be generated. afeintst (00h, 01h) afe interrupt status register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. see the following individual bit definitions for write restriction. afeintst.0Cidr1 ch1 data ready interrupt flag. this bit is set to 1 when a new conversion result is available. this bit remains set unless cleared by software. afeintst.1Cidr2 ch2 data ready interrupt flag. this bit is set to 1 when a new conversion result is available. this bit remains set unless cleared by software. afeintst.2Ciwup1 ch1 wake-up event interrupt flag. this bit is set to 1 when a wake-up condition is detected. this bit remains set unless cleared by software. afeintst.3Ciwup2 ch2 wake-up event interrupt flag. this bit is set to 1 when a wake-up condition is detected. this bit remains set unless cleared by software. afeintst[7:4] reserved. read returns 0.
MAX1441 automotive, two-channel proximity and touch sensor 27 table 11. special-function register bit description (continued) register description sct (01h, 01h) single conversion register (8-bit register) initialization this register is cleared to 02h on all forms of reset. read/write access unrestricted read/write. see the following individual bit definitions for write restriction. sct.0Csct single conversion trigger. setting this bit to 1 initiates a conversion to an enabled channel (pdx = 0) when the single conversion mode is enabled. once set to 1, a write to this bit is ignored. this bit is automatically cleared to 0 at the end of the conversion. sct.1Cscen single conversion enable. setting this bit to 1 enables the single conversion mode. clearing this bit to 0 disables the single conversion mode. sct[7:2] reserved. read returns 0. crng (02h, 01h) input range register (8-bit register) initialization this register is cleared to 22h on all forms of reset. read/write access unrestricted read/write. crng[1:0]C crng1[1:0] ch1 capacitance input range bits [1:0]. these bits set the capacitance input range. crng1[1:0] capacitance range (pf) 00 5 01 10 10 20 11 20 crng[3:2] reserved. read returns 0. crng[5:4]C crng2[1:0] ch2 capacitance input range bits [1:0]. these bits set the capacitance input range. crng2[1:0] capacitance range (pf) 00 5 01 10 10 20 11 20 crng[7:6] reserved. read returns 0. pd (03h, 01h) power-down register (8-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read. write to this register is unrestricted, unless otherwise stated in the following bit definition. pd.0Csb standby enable. setting this bit to 1 enables the standby mode for both channels. clearing this bit to 0 disables the standby mode. when standby mode is enabled, the conversion occurs at a divided-down rate as defined by dsb and ssb. once set, this bit can be cleared by software. this bit is automatically cleared to 0 if a wake-up event occurs. pd.1Cpd1 ch1 power-down. setting this bit to 1 powers down ch1. clearing this bit to 0 powers up ch1. pd.2Cpd2 ch2 power-down. setting this bit to 1 powers down ch2. clearing this bit to 0 powers up ch2. pd[7:3] reserved. read returns 0. wu1 (04h, 01h) ch1 wake-up control register (8-bit register) initialization this register is cleared to 04h on all forms of reset. read/write access unrestricted read/write. wu1.0Cae1 ch1 absolute wake-up threshold enable. setting this bit to 1 enables the absolute wake-up threshold detection. clearing this bit to 0 disables the absolute wake-up threshold detection.
MAX1441 automotive, two-channel proximity and touch sensor 28 table 11. special-function register bit description (continued) register description wu1.1Cre1 ch1 rate-of-change wake-up threshold enable. setting this bit to 1 enables the rate-of-change wake-up threshold detection. clearing this bit to 0 disables the rate-of-change wake-up threshold detection. wu1.2Cao1 ch1 and/or mode enable. setting this bit to 1 causes an interrupt to the cpu when both the absolute and rate-of-change threshold are exceeded. both aei and rei must be enabled when ao1 is set to 1. clearing this bit to 0 causes an interrupt to the cpu when either the absolute threshold or rate-of-change threshold is exceeded. wu1[7:3] reserved. read returns 0. wu2 (05h, 01h) channel 2 wake-up control register (8-bit register) initialization this register is cleared to 04h on all forms of reset. read/write access unrestricted read/write. wu2.0Cae2 ch2 absolute wake-up threshold enable. setting this bit to 1 enables the absolute wake-up threshold detection. clearing this bit to 0 disables the absolute wake-up threshold detection. wu2.1Cre2 ch2 rate-of-change wake-up threshold enable. setting this bit to 1 enables the rate-of-change wake-up threshold detection. clearing this bit to 0 disables the rate-of-change wake-up threshold detection. wu2.2Cao2 ch2 and/or mode enable. setting this bit to 1 causes an interrupt to the cpu when both the absolute and rate-of-change threshold are exceeded. clearing this bit to 0 causes an interrupt to the cpu when either the absolute or rate-of-change threshold is exceeded. wu2[7:3] reserved. read returns 0. fel (06h, 01h) excitation frequency low-limit register (8-bit register) initialization this register is set to 1eh on all forms of reset. read/write access unrestricted read/write. fel[5:0] excitation frequency low-limit bits [5:0]. these bits set the lower end of the excitation frequency (fel x 10khz). fel[7:6] reserved. read returns 0. feb (07h, 01h) excitation frequency spread-spectrum bandwidth register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. feb[4:0] excitation frequency spread-spectrum bandwidth bits [4:0]. these bits set the excitation frequency bandwidth (feb x 20khz). feb[7:5] reserved. read returns 0. crslt1l (08h, 01h) channel 1 conversion result register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access this register is read only. crslt1l.0Covr1 ch1 overrange flag. the overrange flag is set to 1 by hardware if the current conversion causes overranging of the cCtoCd conversion. this bit is cleared to 0 if the current conversion does not cause overranging. crslt1l[3:1] reserved. read returns 0. crslt1l[7:4] channel 1 conversion result bits[3:0]. this register contains the lower 4 bits of the cCtoCd conversion.
MAX1441 automotive, two-channel proximity and touch sensor 29 table 11. special-function register bit description (continued) register description crslt1h (09h, 01h) channel 1 conversion result register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access this register is read-only. crslt1h[7:0] channel 1 conversion result bits[11:4]. this register contains the upper 8 bits of the cCtoCd conversion. crslt2l (0ah, 01h) channel 2 conversion result register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access this register is read-only. crslt2l.0Covr2 ch2 overrange flag. the overrange flag is set to 1 by hardware if the current conversion causes overranging of the cCtoCd conversion. this bit is cleared to 0 if the current conversion does not cause overranging. crslt2l[3:0] reserved. read returns 0. crslt2l[7:4] channel 2 conversion result bits [3:0]. this register contains the lower 4 bits of the cCtoCd conversion. crslt2h (0bh, 01h) channel 2 conversion result register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access this register is read only. crslt2h[7:0] channel 2 conversion result bits [11:4]. this register contains the upper 8 bits of the cCtoCd conversion. at1h (0ch, 01h) ch1 absolute wake-up threshold register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. at1h[7:0] ch1 absolute wake-up threshold bits [11:4]. this register contains the threshold value against which a wake-up event is generated in standby mode. this register has no effect if the absolute threshold is not enabled. rt1h (0dh, 01h) ch1 rate-of-change wake-up threshold register (8-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. rt1h[7:0] ch1 rate-of-change wake-up threshold bits [11:4]. this register contains the threshold value against which a wake-up event is generated in standby mode. this register has no effect if the rate-of-change threshold is not enabled. at2h (0eh, 01h) ch2 absolute wake-up threshold register (8-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. at2h[7:0] ch2 absolute wake-up threshold bits [11:4]. this register contains the threshold value against which a wake-up event is generated in standby mode. this register has no effect if the absolute threshold is not enabled. rt2h (0fh, 01h) ch2 rate-of-change wake-up threshold register (8-bit register) initialization this register is cleared to 0000h on all forms of reset. read/write access unrestricted read/write. rt2h[7:0] ch2 rate-of-change wake-up threshold bits [11:4]. this register contains the threshold value against which a wake-up event is generated in standby mode. this register has no effect if the rate-of-change threshold is not enabled.
MAX1441 automotive, two-channel proximity and touch sensor 30 table 11. special-function register bit description (continued) register description co1 (10h, 01h) channel 1 capacitance offset register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. co1[5:0] channel 1 capacitance offset bits [5:0]. these bits select the amount of capacitance compensation to be applied. capacitance can be adjusted in a 1pf increment up to 63pf. co1[7:6] reserved. read returns 0. co2 (11h, 01h) channel 2 capacitance offset register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. co2[5:0] channel 2 capacitance offset bits [5:0]. these bits select the amount of capacitance compensation to be applied. capacitance can be adjusted in a 1pf increment up to 63pf. co2[7:6] reserved. read returns 0. dsb (12h, 01h) standby state conversion rate divider register (8-bit register) initialization this register is cleared to 01h on all forms of reset. read/write access unrestricted read/write. dsb[4:0] standby state conversion rate divider bits [4:0]. these bits set the conversion rate divider for both channels 1 and 2 in the standby state. the conversion rate is reduced by dsb[4:0]. dsb[7:5] reserved. read returns 0. ssb2 (13h, 01h) channel 2 standby state conversion rate subdivider register (8-bit register) initialization this register is cleared to 01h on all forms of reset. read/write access unrestricted read/write. ssb2[4:0] channel 2 standby state conversion rate divider bits [4:0]. these bits set the additional channel 2 conversion rate divider that is applied, in addition to the dsb divide ratio in the standby state. the con - version rate for channel 2 is divided by dsb[4:0] x ssb2[4:0]. ssb2[7:5] reserved. read returns 0. afeie (14h, 01h) afe interrupt enable register (8-bit register) initialization this register is cleared to 00h on all forms of reset. read/write access unrestricted read/write. afeie.0Cedr1 ch1 data ready interrupt enable. setting this bit to 1 generates an interrupt to the cpu when the idr1 bit is set to 1. clearing this bit to 0 disables an interrupt from generating. afeie.1Cedr2 ch2 data ready interrupt enable. setting this bit to 1 generates an interrupt to the cpu when the idr2 bit is set to 1. clearing this bit to 0 disables an interrupt from generating. afeie.2Ceiwup1 ch1 wake-up event interrupt enable. setting this bit to 1 generates an interrupt to the cpu when eiwup1 = 1. clearing this bit to 0 disables an interrupt from generating. afeie.3Ceiwup2 ch2 wake-up event interrupt enable. setting this bit to 1 generates an interrupt to the cpu when eiwup2 = 1. clearing this bit to 0 disables an interrupt from generating. afeie[7:4] reserved. read returns 0.
MAX1441 automotive, two-channel proximity and touch sensor 31 memory organization there are three distinct memory areas in the ic's regis - ters, program memory, and data memory. all memories are located on-chip. data memory is realized by sram memory, which allows both read and write access; program memory is imple - mented with nonvolatile flash memory. the user applica - tion codes are programmed using a bootstrap loader. the bootstrap loader program is located in the utility code space. from a user perspective, the utility code segment is a program segment in the program memory map. as illustrated in figure 3, the device incorporates 4kb program memory, 4kb utility rom, and 128 bytes sram data memory. data memory is contiguous from 0000h to 03fh words. programmable memory begins at address 0000h and is contiguous through a maximum of 7ffh words. the device also incorporates a soft stack using data ram for the stack. the mmu provides access controls for program and data memories. the built-in bootstrap loader is used to support flash memory erase/program operations. register space two of the register modules (m0/m1) are used by the device. data memory on-chip data memory begins at address 0000h and is contiguous through the internal data memory space to 03fh words (128 bytes). data memory mapping and access control are handled by the mmu. read/write access to the data memory can be in word or in byte. program memory the program memory is implemented using nonvola - tile flash memory. flash memory provides in-system programming capability but this memory technology requires erase operation before a write operation and the time required to carry out write access is extremely long. write access to nonvolatile memory is actually performed by utility rom code for the device . figure 3. memory map sfrs 00h 06h 07h registers sprs 0fh 1fh ffh 0000h 0000h 0000h 003fh 007fh 07ffh 8000h 87ffh ffffh program space 2k x 16 utility code 2k x 16 program memory 64 x 16 data ram data space wbsn = 1 ffffh wbsn = 0 ffffh
MAX1441 automotive, two-channel proximity and touch sensor 32 utility code a program segment on top of the 32k program memory space is realized by rom, which provides system utility functions: ? reset vector ? bootstrap function for system initialization ? in-circuit debug reset vector is located in the utility code, starting at 8000h. following each reset, the processor automatically starts execution from the utility code, allowing the utility code to perform any necessary system-support functions. note that the default value for the instruction pointer is effectively set to the lowest address of the program memory; a reset forces the program address to 8000h directly and activates the utility code for code fetch. the most significant bit of the address bus continues to be held high until the program flow is first progressed out - side the utility code memory range. the spe bit can be used to force the processor to bypass the utility code reset routine and start execution from the user code after a reset. the device is always reset to 8000h after a reset. if the spe bit is cleared to logic 0, the processor vectors out of the utility code segment immedi - ately and starts standard user-program execution at loca - tion 0000h of the program memory. however, if the spe bit is set to logic 1, the processor starts execution from the utility code, entering to the bootstrap loader mode. the spe bit is defaulted to 0. to enter the bootstrap loader mode, the spe bit can be set during por using the jtag interface. the bootstrap loader should clear the spe bit to 0 after program initialization. if the utility code is bypassed during reset, the initializa - tion vector should be stored in the lower bytes of the program memory. nonvolatile memory programming the program memory is realized in the flash memory, which provides a storage area for critical code/data that must be maintained in case of power-down. write access to the nonvolatile memory is performed by a utility code routine that is initiated by a user call to the subroutine. the rom routine can perform the write to the flash. program stack the device supports only a software stack that is located in the normal data memory space and its contents are fixed as 16-bit words. the program stack supports sub - routine calls and system interrupts. the stack can also be used to store variables by the user software. the program stack is addressed by the stack pointer (sp). the sp designates the stack location at the top of the stack, which is the location of the last word stored. the sp register is a 16-bit register but only the lower bits are implemented as per c_sp_len configuration. the sp is defaulted to 02f0h and the content of the sp is predec - remented for write and postincremented for read. the sp value is automatically decreased before a write opera - tion, and automatically increased after a read operation. note that the push and pop instructions are provided for the convenience of programmers who prefer to use these traditional stack-related instructions. from the assembly and the hardware point of view, the push and pop instructions are equivalent to the move @++sp, xxx and move xxx, @sp-- instruction, respectively. these move instructions involved with indirect sp predecrement/ postincrement the sp register value accordingly. memory management unit memory allocation and access control for program and data memories are managed by the mmu. program stack is controlled by a dedicated state machine for fast stack operation. the instruction pointer is fully decoded. access to any nonexisting physical memory returns nop. the instruc - tion pointer keeps increasing until it reaches 0ffffh (top of ip), then it wraps around to 0000h. the data pointer is fully decoded. access to any nonex - isting physical memory returns a value of 0. if an instruc - tion requests the data pointer to be increased, it keeps increasing until it reaches 0ffffh (top of dp), then it wraps around to 0000h. if an instruction requests the data pointer to be decreased, it keeps decreasing until it reaches 0000h, then it wraps around to 0ffffh. the last word in sector 1 (07ffh) is used as a security lock. when content of the security word[15:0] is equal to ffffh, the memory is unsecured and program and erase operations are allowed. when security word[15:0] is any other value, all memory write operations are blocked by the hardware. caution: do not write any value other than ffffh in memory location 07ffh (last word of the flash memory). any value other than ffffh in this location permanently secures the flash memory and no fur - ther flash write or erase operations are allowed. all erase/program operations are under the control of the flash controller and assisted by the rom code.
MAX1441 automotive, two-channel proximity and touch sensor 33 the device does not support individual word programming. a whole page must be programmed at the same time. in attempts to write to an individual word, the data intended for the individual word is copied to the entire page. caution: it is the users responsibility to ensure that a flash high-voltage operation (erase or write) is allowed to complete without external intervention. when an external intervention such as por, or asserting the reset pin, is applied during a flash high-voltage operation, the flash operation is aborted. this can cause irreversible dam - age to the flash and make the flash inoperable. instruction set the device supports all the standard maxq20 instructions when executing from flash and the utility rom (table 12). for a complete list of instructions and detailed descriptions, refer to the maxq family instruction set summary in the maxq family users guide. table 12. maxq family instruction set summary mnemonic description 16-bit instruction word status bits affected ap inc/dec notes logical operations and src acc acc and src f001 1010 ssss ssss s, z y 4 or src acc acc or src f010 1010 ssss ssss s, z y 4 xor src acc acc xor src f011 1010 ssss ssss s, z y 4 cpl acc ~acc 1000 1010 0001 1010 s, z y neg acc ~acc + 1 1000 1010 1001 1010 s, z y sla shift acc left arithmetically 1000 1010 0010 1010 c, s, z y sla2 shift acc left arithmetically twice 1000 1010 0011 1010 c, s, z y sla4 shift acc left arithmetically four times 1000 1010 0110 1010 c, s, z y rl rotate acc left (w/o c) 1000 1010 0100 1010 s y rlc rotate acc left (through c) 1000 1010 0101 1010 c, s, z y sra shift acc right arithmetically 1000 1010 1111 1010 c, z y sra2 shift acc right arithmetically twice 1000 1010 1110 1010 c, z y sra4 shift acc right arithmetically four times 1000 1010 1011 1010 c, z y sr shift acc right (0 msbit) 1000 1010 1010 1010 c, s, z y rr rotate acc right (w/o c) 1000 1010 1100 1010 s y rrc rotate acc right (though c) 1000 1010 1101 1010 c, s, z y bit operations move c, acc. c acc. 1110 1010 bbbb 1010 c move c, #0 c 0 1101 1010 0000 1010 c move c, #1 c 1 1101 1010 0001 1010 c cpl c c ~c 1101 1010 0010 1010 c move acc., c acc. c 1111 1010 bbbb 1010 s, z and acc. c c and acc. 1001 1010 bbbb 1010 c or acc. c c or acc. 1010 1010 bbbb 1010 c xor acc. c c xor acc. 1011 1010 bbbb 1010 c move dst., #1 dst. 1 1ddd dddd 1bbb 0111 c, s, e, z 5 move dst., #0 dst. 0 1ddd dddd 0bbb 0111 c, s, e, z 5 move c, src. c src. fbbb 0111 ssss ssss c math add src acc acc + src f100 1010 ssss ssss c, s, z, ov y 4 addc src acc acc + (src + c) f110 1010 ssss ssss c, s, z, ov y 4 sub src acc acc C src f101 1010 ssss ssss c, s, z, ov y 4 subb src acc acc C (src + c) f111 1010 ssss ssss c, s, z, ov y 4
MAX1441 automotive, two-channel proximity and touch sensor 34 table 12. maxq family instruction set summary (continued) note 4: the active accumulator (acc) is not allowed as the src in operations where it is the implicit destination. note 5: bit operation. potentially affects c or e if the psf register is the destination. potentially affects s and/or z if ap or apc is the destination. note 6: the {l/s} prefix is optional. note 7: instructions that attempt to simultaneously push/pop the stack (e.g., push @sp--, push @spi--, pop @++sp, popi @++sp) or modify sp in a conflicting manner (e.g., move sp, @sp--) are invalid. note 8: special cases: if move apc, acc sets the apc.clr bit, ap is cleared, overriding any auto-inc/dec/modulo operation specified for ap. if move ap, acc causes an auto-inc/dec/modulo operation on ap, this overrides the specified data transfer (i.e., acc is not transferred to ap). mnemonic description 16-bit instruction word status bits affected ap inc/dec notes branching {l/s}jump src ip ip + src or src f000 1100 ssss ssss 6 {l/s}jump c, src if c=1, ip (ip + src) or src f010 1100 ssss ssss 6 {l/s}jump nc, src if c=0, ip (ip + src) or src f110 1100 ssss ssss 6 {l/s}jump z, src if z=1, ip (ip + src) or src f001 1100 ssss ssss 6 {l/s}jump nz, src if z=0, ip (ip + src) or src f101 1100 ssss ssss 6 {l/s}jump e, src if e=1, ip (ip + src) or src 0011 1100 ssss ssss 6 {l/s}jump ne, src if e=0, ip (ip + src) or src 0111 1100 ssss ssss 6 {l/s}jump s, src if s=1, ip (ip + src) or src f100 1100 ssss ssss 6 {l/s}djnz lc[n], src if --lc[n] <> 0, ip (ip + src) or src f10n 1101 ssss ssss 6 {l/s}call src @++sp ip+1; ip (ip+src) or src f011 1101 ssss ssss 6, 7 ret ip @sp-- 1000 1100 0000 1101 ret c if c=1, ip @sp-- 1010 1100 0000 1101 ret nc if c=0, ip @sp-- 1110 1100 0000 1101 ret z if z=1, ip @sp-- 1001 1100 0000 1101 ret nz if z=0, ip @sp-- 1101 1100 0000 1101 ret s if s=1, ip @sp-- 1100 1100 0000 1101 reti ip @sp-- ; ins 0 1000 1100 1000 1101 reti c if c=1, ip @sp-- ; ins 0 1010 1100 1000 1101 reti nc if c=0, ip @sp-- ; ins 0 1110 1100 1000 1101 reti z if z=1, ip @sp-- ; ins 0 1001 1100 1000 1101 reti nz if z=0, ip @sp-- ; ins 0 1101 1100 1000 1101 reti s if s=1, ip @sp-- ; ins 0 1100 1100 1000 1101 data transfer xch (maxq20 only) swap acc bytes 1000 1010 1000 1010 s y xchn swap nibbles in each acc byte 1000 1010 0111 1010 s y move dst, src dst src fddd dddd ssss ssss c, s, z, e (note 8) 7, 8 push src @++sp src f000 1101 ssss ssss 7 pop dst dst @sp-- 1ddd dddd 0000 1101 c, s, z, e 7 popi dst dst @sp-- ; ins 0 1ddd dddd 1000 1101 c, s, z, e 7 cmp src e (acc = src) f111 1000 ssss ssss e nop no operation 1101 1010 0011 1010
MAX1441 automotive, two-channel proximity and touch sensor 35 special system functions interrupt the device supports interrupt through the interrupt vector (iv) register and the interrupt control (ic) register. the iv register allows the user program to set a preferred vector location to any program memory address. the iv register is fixed at 07fdh. since the reset location can also be at 0000h, the user program must take care of any potential conflict between the reset and interrupt vector function. interrupt sources interrupt sources can be classified into two categories: ? asynchronous interrupt ? synchronous interrupt the device supports the following asynchronous inter - rupts: ? external interrupts ? watchdog interrupt ? timer interrupts ? afe interrupts all the other internal interrupts are synchronous inter - rupts. synchronous internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle. clock generation all functional units in the device are synchronized to the system clock that is generated from the 20mhz oscillator. the basic unit of time in the device is the sys - tem clock period. all storage logic blocks are triggered by the rising edge of the system clock. clock sources the internal clock circuitry generates the system clock from an internal 5mhz, which is derived from the 20mhz oscillator (figure 4). each time-code execution must start or restart (e.g., exiting stop mode), the following sequence occurs: 1) remove clock gating of internal 5mhz. 2) reset the warm-up counter. 3) wait for flash to power up (about 10 fs). 4) allow the required warm-up delay of eight oscillator cycles of the 5mhz input. the only time 20mhz turns off is if the cpu is in stop mode and afe is in standby mode or powered down (pd register = 6). during stop mode, if the afe is in standby mode, the oscillator is periodically turned off and on to allow the afe to sample inputs. this causes an interrupt to the cpu if an enabled threshold condition is met. figure 4. clock sources 20mhz oscillator xdog startup timer flash controller /4 por stop 1.25mhz stop reset por /4 xdog_done system clock 5mhz system clock generation
MAX1441 automotive, two-channel proximity and touch sensor 36 watchdog timer the watchdog timer is clocked by the internal 32khz oscillator (table 13). all timing reference for the watch - dog is based on the 32khz. in addition, the watchdog is disabled in debug mode and when spe is set to 1. clock to the watchdog is gated off in the conditions mentioned in the clock sources section. startup timer an independent startup timer (x-dog timer) functions: ? when the device is first powered up (por) ? exis from stop mode the x-dog counter is used to count eight oscillator cycles of the 5mhz after the power supply is stable. the power supply is stable after three-to-four 32khz oscillator cycles. the afe circuit is released at least one 32khz oscillator cycle before the cpu to allow for the 5mhz clock startup to properly occur. the x-dog timer is active only for startup count; during normal operation, it is completely shut off. idle mode the device supports idle mode. idle mode suspends the processor by holding the instruction pointer (ip) in a static state. no instructions are fetched and no process - ing occurs. setting the idle bit in the sc register to logic 1 invokes the idle mode. the instruction that executes this step is the last instruction prior to freezing the program counter. once in idle mode, all resources are preserved and all clocks remain active with the enabled peripherals. the power monitor continues to work, so the processor can exit the idle state using any of the inter - rupt sources that are enabled. the idle bit is cleared automatically once the idle state is exited, allowing the processor to execute the instruction that immediately follows the instruction that sets the idle bit. resetting the processor also removes the idle mode. reset places the processor in a reset state and clears the idle bit. stop mode the stop mode disables all circuits within the processor, unless explicitly stated otherwise. all microcontroller system clocks, timers, and serial communication are stopped and no processing is pos - sible. however, the afe can be left in the standby mode and remain functional. once in stop mode, the cpu is in a static state. its power consumption is mostly limited by the leakage current. stop mode is invoked by setting the stop bit to logic 1. the processor enters the stop mode on the instruction that sets the stop bit. entering the stop mode does not affect the setting of the clock control bits. this allows the system to return to its original operating frequency following the stop mode removal, except if the removal is caused by rst or a power loss, which resets the clock generation to its default condition. the processor can exit stop mode by: ? any of the external interrupts that are enabled. ? external reset using the rst pin. ? timer interrupt. ? watchdog timeout. ? afe interrupts that are enabled. when the stop mode is removed, the device executes the following procedure: 1) remove clock gating of internal 5mhz. 2) reset the warm-up counter. 3) wait for flash to power up (about 10 fs). 4) allow the required warm-up delay of eight oscillator cycles of the 5mhz input. 5) resume normal operation. during stop mode, the following peripherals can be operational: ? timer (tmren = 1) ? watchdog timer (wdcn.ewdi = 1) ? afe reset conditions the device has four ways of entering a reset state: ? power-on reset ? watchdog timer reset ? external reset ? internal system reset table 13. watchdog timer timeout interval wd[1:0] timeout count timeout (s) 00 16384 0.5 01 32768 1.0 10 65536 2.0 11 131072 4.0
MAX1441 automotive, two-channel proximity and touch sensor 37 if the reset is caused by watchdog or external sources, the clock source (5mhz oscillator) remains running, but no program execution is allowed. when the reset source is external, the user must remove the reset stimulus. when power is applied to the device, the power-on delay removes the stimulus automatically. power-on reset generation the device incorporates an internal voltage reference and comparator to monitor v dd and hold the device in reset if the supply is out of tolerance. once v dd has risen above the v por threshold, the device generates a power-on reset, starts the internal 20mhz, and counts eight cycles of the derived 5mhz to ensure that flash is powered up and the system clock source has had time to stabilize. the processor then exits the reset state automatically and starts executing the program at loca - tion 8000h. software can determine that a por has occurred by checking the power-on reset flag, por in the wdcn register. software should clear the por flag after having read it. the por is an asynchronous reset source. watchdog timer reset the watchdog timer is a free-running timer with a programmable interval. the watchdog supervises the processor operation by requiring software to clear the timer counter before the timeout expires. if the timer is enabled and software fails to clear it before this interval expires, the device is placed into a reset state. the reset state maintains for about 90 system clock cycles. once the reset is removed, the processor resumes execution at address 8000h. software can determine if a reset is caused by a watchdog timeout by checking the watch - dog timer reset flag, wtrf in the wdcn register. this flag is cleared by software only. external reset if the reset input is taken to logic 0, the device is forced into a reset state. an external reset is accomplished by holding the reset pin low at least four clock cycles while the internal 5mhz clock is running. once the reset state is invoked, it is maintained as long as reset is pulled to logic 0. when the reset state is removed, the processor exits the reset state within four clock cycles and begin execution at address 8000h. if a reset state is applied while the processor is in the stop mode, the reset causes the processor to exit the stop mode and forces the program counter to 8000h. the reset delay is four clock cycles. the reset is a bidirectional i/o. if a reset is caused by a watchdog timer reset or an internal system reset, an output reset pulse is also generated at the reset pin. this reset pulse is asserted as long as a reset source is asserted and may not be able to drive the reset signal out if the reset pin is connected to an rc reset circuitry. connecting the reset pin to a capacitor would not affect the internal reset condition. internal system reset an internal system reset can occur in system program - ming mode when the rod bit is set to logic 1 while the spe bit is 1. timer the device has implemented an 8-bit timer with an 11-bit prescaler. the operation of the timer is configurable using the timer control register (tcon), timer frequency register (tfrq), and the timer counter register (tcnt). the timer is enabled by setting the timer enable bit (tcon.tmren) to 1. once enabled, the timer starts counting from the initial tcnt value up to the tfrq limit. when tcnt = tfrq, the timer interrupt flag (tmrif) is set to 1. this can cause an interrupt to the cpu if the timer interrupt is enabled (tmrie = 1). once the frequency limit is reached, tcnt is reset to 0 and continue to count up again. the timer has two clock sources: system clock and the 32khz clock. the selection is made using the timer clock select (tclk) bit. due to different clock domains, when running off the 32khz clock, reading of the tcnt register is only valid when the timer valid flag (tvalid) is set to 1. when running the system clock, there is no restriction on running from tclk. in addition, a write to trmen when running off the 32khz clock can be delayed due to synchronization between the two domains. to increase the period between subsequent interrupts, an 11-bit prescaler is provided to prescale the input clock from 1 to 2048. if the timer is enabled and running off the 32khz clock source prior to the stop mode entry, the timer continues to run and invoke a stop mode exit if the interrupt is enabled.
MAX1441 automotive, two-channel proximity and touch sensor 38 i/o ports the device implements an i/o port that is slightly differ - ent from those found in other maxq products. the i/o port is still governed by the pi0, po0, and pd0 registers. when a pd0 register is cleared to 0, the port pin is oper - ating as input and the pin is high impedance. the pi register contains the input value. pi is read only. pi may not always immediately equal po due to capacitance at the output. when a pd0 bit is set to 1, the output is enabled and the port pin output data corresponds to the po value. in addition, p0.5 and p0.6 can only be used as open- drain outputs. to use p0.5 and p0.6, clear po bit to 0 and drive pd bit with inverted data. when used as inputs, do not leave the port unconnect - ed. program unused port pins as outputs. the external interrupt flag (eif) is set to 1 when either a rising or falling edge is detected on a port pin regardless of its pd0 value. an interrupt is generated if it is enabled (eie = 1). at power-up, weak pullups are enabled on pin p0.[4:0]. to disable a pullup, clear the associated bit in the po0 register. the external interrupts are asynchronous. peripheral prioritization in the discussion that follows, priority only has mean - ing when two peripherals are both configured to drive outputs at the same time. then one of the named peripherals output has priority over the other, thus making the others output disabled. note that the lower priority peripheral can still be running and trying to output value onto the pad. however, since it has lower priority, its output is not driven onto the pad. for inputs, all peripherals have equal priorityeven though the inputs may not be desirable. this means that if two input peripherals sharing the same pin are enabled, both of them receive the same input concurrently. when a pin operates as input (whether it is a gpio or special-function input), its behavior is governed by po0 and pd0. anytime a pin behaves as an output (because one of its special functions is configured as output), po0 and pd0 are no longer used. port 0 supports the following functions: jtag and gpio. all special functions have priority over gpio. jtag pin special function the following apply when port pins are multiplexed with the jtag function: ? the special-function enable (sf enable) signal for these jtag pins must be active during reset so that the jtag port is accessible during this time. sf enable is controlled by the tap register bit, which is set to 1 on all resets. ? the special-function input, when disabled, should be gated high for tms. this disables the jtag interface and forces the tap into the test-logic-reset state if the tck pin has been toggled for more than five times. ? the tdo special-function enable requires not only that tap = 1, but also that the tap be in the shift-ir or shift-dr state. the debug engine already produces a control signal (tdonz) to denote when the tap is in a shift state. system operating modes following each system reset, the device automatically activates the utility rom at 8000h. the reset vector in the utility rom determines whether the program flow is to start in the user mode or the rom bootstrap mode. the factor that determines which program is executed is the system programming enable (spe) bit in the icdf reg - ister. the spe can be set/cleared with the debug mode command using the tap interface. the device supports various modes of system opera - tions. normally, the device is running in user mode to support user applications. the rom bootstrap load - er mode is used for initializing memory and system configuration. the debug mode is intended to provide real-time in-circuit debugging/emulation. the debug mode is supported through a test access port (tap) and the tap controller, which is compatible to the jtag standard. the tap and the tap controller are enabled after any reset, but remain inactive until a valid command is entered into the instruction register so as not to disrupt normal user-mode operation. if the tap is not used, or the tap interface pins are needed to serve another purpose, the tap can be disabled by clearing the tap enable (tap) bit located in the sc system register. depending upon the mode desired, the instruction regis - ter should be loaded with the associated "debug" or "in- system programming" instruction. the method for loading the instruction register is described in the subsequent sections. these modes can be established anytime the digital supply voltage is above the por threshold (e.g., during system reset both are acceptable).
MAX1441 automotive, two-channel proximity and touch sensor 39 jtag port the device supports a tap and tap controller for communication with a bus master that can be either an automatic test equipment or a component that interfaces to a higher level test bus as part of a complete system. the communication operates across a 4-wire serial interface from a dedicated tap, which is compatible to the jtag ieee m standard 1149. the tap is a general- purpose port, which allows access to many debug and test functions built into the core. for detailed information on the tap and tap controller, refer to ieee standard 1149.1 ieee standard test access port and boundary-scan architecture . bootstrap loader mode internal nonvolatile memory can be initialized by the bootstrap loader in bootstrap loader mode. the boot - strap loader mode is enabled by an external host device using the tap in the system programming instruction. the system programming function is supported using the system programming buffer (spb): 1) spb.0Csystem programming enable (spe) when it is set, the bootstrap loader program is activated to perform a bootstrap loader function. when it is cleared, the reset vector forces the ip to 8000h and starts normal user-program execution. 2) spb.2:1Cprogramming source select (pss[1:0]) these bits allow the host to select programming inter - face sources: user mode user applications are executed in user mode. in user mode, the processor can execute program routines in any memory segments. normally, data is loaded and stored from/to the data memory. the device contains three mem - ory segments among the program and the data spaces: ? program segment ? data segment ? utility rom segment password-protected access some applications require preventive measures to pro - tect against simple access and viewing of program code memory. to address this need for code protection, the device grants full access to in-system programming or in-circuit debugging utilities only after a password has been supplied. the password is defined as the 16 words of physical program memory at addresses 0010h to 001fh. note that using these memory locations for a password does not exclude their usage for general code space if a unique password is not needed. also, if addresses 0010h to 001fh contain all zeros or all ffffs, the password function is effectively disabled and a pass - word is not needed to gain access. a single password lock bit (pwl) is implemented in the sc register. when the pwl is set to 1, a password is required to access the rom loader utilities, which sup - port read/write accessing of internal memory and debug functions. when pwl is cleared to 0, these utilities are fully accessible through the utility rom without a password. the pwl bit defaults to 1 by a por. to access the rom utilities, a correct password is needed; otherwise, access of rom utilities is denied. once the correct password has been supplied by the user, the rom utility clears the password lock. the pwl remains clear until one of the following occurs: ? a power-on reset or ? set to logic 1 by user software. entering password a password can be entered: ? using the interface established by the pss1 and pss0 bits in system programming when the spe bit is set to logic 1; the rom loader must establish a suitable protocol for that interface to recognize the multibyte password. or ? through the tap interface directly in debug mode or test mode by issuing a password-unlock command; this command requires 32 follow-on transfer cycles, each containing a byte value compared with the password. ieee is a registered service mark of the institute of electrical and electronics engineers, inc. pss1 pss0 programming source 0 0 jtag 0 1 reserved 1 0 reserved 1 1 reserved
MAX1441 automotive, two-channel proximity and touch sensor 40 applications information layout, grounding, and bypassing for best performance, use pcbs. ensure to separate digital and analog signal lines from each other. do not run analog and digital signals parallel to one another (especially clock signals) or do not run digital lines underneath the ic package. high-frequency noise in the power-supply lines can affect performance. bypass the v aa and v dd supplies with 0.47 f f capacitors close to v aa and v dd . bypass the v batt supply with a 0.1 ff capacitor close to the v dd pin. minimize capacitor lead lengths for best supply-noise rejection. refer to the MAX1441 evaluation kit for an example of proper layout. chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern n o. 20 tssop u20m+2 21-0066 90-0116
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 41 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX1441 automotive, two-channel proximity and touch sensor revision history revision number revision date description pages changed 0 6/10 initial release

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